The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having an array of basic circuits having bipolar transistors, and a test circuit for testing logic circuits formed of the basic circuits.
Semiconductor integrated circuit devices having bipolar transistors are high-speed devices and are widely used in high-performance digital systems, such as large scale computers for the general purpose and wide frequency range transmission systems. Recently, there has been considerable activity in the development of larger scale and higher speed bipolar semiconductor integrated circuit devices in order to further improve high-performance digital systems. Such a bipolar semiconductor integrated circuit device has a larger ratio of the number of internal gates to the number of external pins. Generally, an increase in the number of internal gates needs a more complicated device testing procedure. Thus, there is a need to provide a bipolar semiconductor integrated circuit device which has a built-in test circuit capable of easily carrying out various tests.
Japanese Laid-Open Patent Application No. 61-42934 (which corresponds to U.S. patent application Ser. No. 760 347, abandoned, continuation application Ser. No. 387,455, now abandoned, of the application Ser. No. 760,347 and divisional application Ser. No. 508,565, now abandoned, of the application Ser. No. 760,347) discloses a semiconductor integrated circuit device having a built-in test circuit. Referring to FIG. 1, the semiconductor integrated circuit device disclosed in the above-mentioned application has a chip body 1, gate cells 2 and a built-in test circuit. The built-in test circuit comprises row select lines 3, column read lines 4, switching elements 5, a row select ring counter 6, a column select ring counter 7, a data selector 8, a row select clock input terminal 9, a column select clock input terminal 10 and a monitor output terminal 11. The routing of interconnections between the gate cells 2 are determined based on the orders from users. Such interconnections for forming logic circuits are not shown for the sake of simplicity.
Output terminals of the gate cells 2 are connected to the column read lines 4 via the switching elements 5. The row select ring counter 6 selects one of the row select lines 3, and the column select ring counter 7 selects one of the column read lines 4, so that one of the gate cells 2 can be selected. Such a selecting procedure is repeatedly carried out. Data about the logical state of the output terminal of the selected gate cell 2 is transferred to the monitor output terminal 11 via the data selector 8.
The above-mentioned testing procedure is called a matrix proving method. Such a matrix proving method has no limitations regarding testing of flip-flops and latches used for forming logic circuits, and can test the logic circuits in a gate cell unit. Thus, the matrix proving method can facilitate the procedure for designing the logic circuits and can achieve high testing reliability, as compared with a conventional scan path method using a scan flip-flop.
FIG. 2 illustrates a conventional TTL circuit device based on the configuration shown in FIG. 1, and FIG. 3 illustrates a conventional MOS circuit device based on the configuration shown in FIG. 1. As shown in FIG. 2, each of the switching elements 5 shown in FIG. 1 is formed of an NPN transistor 12 and a resistor 13. As shown in FIG. 3, each of the switching elements shown in FIG. 1 is formed of an n-channel MOS transistor 14. The configurations shown in FIGS. 2 and 3 are also disclosed in the aforementioned Japanese application. It is noted that similar circuits are disclosed in D. K. Jadus, et al., "TEST PAD MULTIPLEXING", IBM Technical Disclosure Bulletin, Vol. 18, No. 7, December 1975, pp.2181-2182, or J. Canard, et al., "VOLTAGE CHECKING DEVICE", IBM Technical Disclosure Bulletin, Vol. 8, No. 5, Oct. 1965, pp.806-807.
However, the Japanese application neither discloses nor suggests a concrete configuration obtained by applying the configuration shown in FIG. 1 to an ECL (emitter coupled logic) circuit device. An ECL circuit device has gate cells formed of ECL circuits, each ECL circuit having an emitter follower circuit at the final stage thereof. If each gate cell 2 shown in FIG. 2 is formed of the ECL circuit, a large amount of current will pass through a load resistor of the emitter follower circuit, so that the output level of the ECL circuit greatly deviates from a normal value, and the entire logic circuit will malfunction. For the above-mentioned reason, it is impossible to use the switching elements consisting of the transistors 12 and the resistors 13 without any improvements when the TTL structure of each gate cell 2 is replaced by the ECL structure.
On the other hand, each gate cell may be formed of the ECL circuit by suitably designing a circuit following the MOS transistors 14. However, the combination of the ECL circuit and the MOS switching element 14 will increase the number of production steps, and will deteriorate the performance of bipolar transistors forming the ECL circuit.